1. Technical Field of the Invention
The present invention relates generally to an analog switch formed from CMOS devices and, more particularly, to a negative analog switch.
2. Description of Related Art
An analog switch circuit, also referred to in the art as a transmission gate, is a widely used basic circuit component. A conventional analog switch circuit is shown in FIG. 1 to include a pair of MOS transistors connected in parallel. More particularly, the analog switch 10 includes a PMOS transistor 12 and an NMOS transistor 14 whose source/drain paths are connected in parallel. The source of the NMOS transistor 14 is connected to the drain of the PMOS transistor 12 to form a first terminal 16 of the analog switch 10. The source of the PMOS transistor 12 is connected to the drain of the NMOS transistor 14 to form a second terminal 18 of the analog switch 10. The PMOS transistor 12 includes first and second body diodes 20 and 22. The NMOS transistor 14 includes first and second body diodes 24 and 26.
The gates of the two transistors 12 and 14 receive control signals to turn on the analog switch and thus connect the first terminal 16 to the second terminal 18. For example, the analog switch is turned on when a positive voltage Vdd is applied to the gate of the NMOS transistor 14 and ground Gnd is applied to the gate of the PMOS transistor 12. The body of the PMOS transistor is connected to the positive voltage Vdd while the body of the NMOS transistor is connected to ground Gnd.
Reference is now made to FIG. 2 which shows operation of the analog switch of FIG. 1 to pass an analog signal. The gate of the PMOS transistor 12 receives a control signal PG_CTL while the gate of the NMOS transistor 14 receives a control signal NG_CTL. An analog signal (for example, of the form shown as a sine wave) is applied to the first terminal 16 (Input). The control signal PG_CTL is set to ground Gnd and the control signal NG_CTL is set to the positive voltage Vdd. Both the PMOS transistor 12 and the NMOS transistor 14 are turned on. If the analog signal at the first terminal 16 falls below −0.7 V, the body diodes 24 and 26 of the NMOS transistor 14 will become forward biased. This will result in a distortion of the signal (as shown) at the second terminal 18 (Output), and further could result in damage to the analog switch 10.
FIG. 3 shows an analog switch circuit which addresses the foregoing problem of the FIG. 1 switch design. The analog switch 30 of FIG. 3 includes a PMOS circuit 32 including first and second PMOS transistors 34 and 36 connected in series. The analog switch further includes an NMOS circuit 38 including first and second NMOS transistors 40 and 42 connected in series. The PMOS circuit 32 and NMOS circuit 38 are connected in parallel. The source of the NMOS transistor 40 is connected to the drain of the PMOS transistor 34 to form a first terminal 44 of the analog switch 30. The source of the NMOS transistor 42 is connected to the drain of the PMOS transistor 36 to form a second terminal 46 of the analog switch 30. The body of PMOS transistor 34 is shorted to the first terminal 44, and a body diode 48 is present between the body of PMOS transistor 34 and a first series connection node 50. The body of PMOS transistor 36 is shorted to the second terminal 46, and a body diode 48 is present between the body of PMOS transistor 36 and the first series connection node 50. The body of NMOS transistor 40 is shorted to the first terminal 44, and a body diode 52 is present between the body of NMOS transistor 40 and a second series connection node 54. The body of NMOS transistor 42 is shorted to the second terminal 46, and a body diode 52 is present between the body of NMOS transistor 42 and the second series connection node 54.
Reference is now made to FIG. 4 which shows operation of the analog switch of FIG. 3 to pass an analog signal. The gates of the PMOS transistors 34 and 36 receive a control signal PG_CTL while the gates of the NMOS transistors 40 and 42 receive a control signal NG_CTL. An analog signal (for example, of the form shown as a sine wave) is applied to the first terminal 44 (Input). The control signal PG_CTL is ground Gnd and the control signal NG_CTL is the positive voltage Vdd. The PMOS transistors 34 and 36 and the NMOS transistors 40 and 42 are turned on. Because of the series connected transistors in each circuit 32 and 38, the voltage drop across each included transistor is less than 0.7 V, so the body diodes 48 and/or 52 do not turn on and there is no distortion of the signal at the second terminal 46 (as shown).
While the FIG. 3 analog switch circuit addresses the problem associated with the FIG. 1 analog switch circuit, a drawback of the FIG. 3 analog switch circuit is that the area required to fabricate the transmission gate circuit between input and output nodes must be much larger than the area of the FIG. 1 analog switch circuit in order to achieve a same on-resistance value. A need exists for an analog switch which addresses the problems of the FIG. 1 circuit and where the transmission gate itself does not require the same die area as the FIG. 3 circuit.